1. Field of the Invention
The present invention relates to a signal processing apparatus having a common line through which a plurality of signals are sequentially read.
2. Related Background Art
A signal transmission circuit for transmitting signals from a plurality of signal sources via signal transfer switches to a common line is used, for example, in a solid state image pickup device.
An example of the solid state image pickup device is an amplification type MOS sensor. In the amplification type MOS sensor, generally, signal charges generated in each pixel are converted into voltage by using a capacitor, and then a signal is read from each capacitor by using a scanning circuit and signal transfer switches, without directly reading the signal charges themselves.
Each pixel of such a solid state image pickup device has a photoelectric conversion unit for generating signal charges corresponding to incidence light and an amplifier unit for performing impedance conversion of a signal voltage converted by a capacitor from the signal charges of the photoelectric conversion unit. The operation of outputting a signal voltage from an output terminal via an amplifier unit and a signal transfer unit of each pixel will be described with reference to FIG. 1 showing a solid state image pickup device with linearly disposed pixels.
In FIG. 1, S1 to Sn represent photoelectric conversion units of pixels. A1 to An represent amplifier units for converting signal charges supplied from the photoelectric conversion units S1 to Sn into voltages and amplifying them. Q1 to Qn represent MOS transistors functioning as switches for transferring signal voltages supplied from the amplifier units A1 to An to sample/hold capacitors CT1 to CTn. The MOS transistors Q1 to Qn turn on when a pulse φ1 applied to a terminal 104 takes a high potential, and turn off at a low potential. Qh1 to Qhn represent MOS transistors as switches which sequentially turn on in response to pulses φh1 to φhn supplied from a scanning circuit and sequentially transfer the signal voltages held by the sample/hold capacitors CT1 to CTn to a horizontal signal line 101. Qhr represents a MOS transistor as a switch which resets the horizontal signal line to a ground level during a period between sequential transfers of the signal voltages from the MOS transistors Qh1 to Qhn to the horizontal signal line 101. The MOS transistor Qhr turns on when a pulse φhr takes the high potential and turns off at the low potential. A buffer amplifier 3 receives the signal voltage on the horizontal signal line 101 and outputs the signal from an output terminal 102.
Although not shown in FIG. 1, the horizontal signal line 101 has a capacitance (hereinafter represented by Ch). This capacitance Ch is a total sum of capacitances Cdbn and Cgdn. The capacitances Cdbn are parasitic capacitances between the source/drain and substrate of the MOS transistors Qh1 to Qhn as the transfer switches and the MOS transistor Qhr as the reset switch. The capacitances Cgdn are called overlapping capacitances and are parasitic capacitances between the source/drain and gate of these transistors.
The operation of the solid state image pickup device will be described further with reference to the timing chart shown in FIG. 2.
During a period T1, the pulses φ1 and φhr take the high potential so that the MOS transistors Q1 to Qn and MOS transistor Qhr turn on. Therefore, the signal voltages are applied from the amplifier units A1 to An to the sample/hold capacitors CT1 to CTn via the MOS transistors Q1 to Qn, and at the same time, the potential of the horizontal signal line 101 takes the ground level. Thereafter, the pulse φ1 takes the low level so that the MOS transistors Q1 to Qn turn off and the output voltages from the amplifier units A1 to An are held in the sample/hold capacitors CT1 to CTn.
Next, during a period T2, the pulse φh1 takes the high potential so that the MOS transistor Qh1 turns on and the charges in the sample/hold capacitor CT1 are transferred to the parasitic capacitor Ch of the horizontal signal line 101. Therefore, the potential of the sample/hold capacitor CT1 is transmitted to the horizontal signal line 101 and a signal voltage is output from the output terminal 102 of the buffer amplifier.
Next, during a period T3, the pulse φhr takes the high potential so that the potential at the horizontal signal line 101 takes the ground level.
Similarly, during periods T4 to T6, the potentials held at the sample/hold capacitors CT2 to CTn are sequentially transmitted to the horizontal signal line 101 and output from the output terminal 102 of the buffer amplifier 3.
A change in the voltage at the output terminal 102 during the periods T1 to T6 is also shown in FIG. 2.
Another example of a conventional solid state image pickup device using clamp capacitors is shown in FIG. 3. The fundamental structure and operation are similar to the solid state image pickup device shown in FIGS. 1 and 2. However, as shown in FIG. 3, the sample/hold capacitors CT1 to CTn are removed from the structure shown in FIG. 1, and clamp capacitors C1 to Cn and MOS transistors Qr1 to Qrn as reset switches are inserted. A control terminal 105 is added for controlling on/off of the MOS transistors Qr1 to Qrn.
In operation of this conventional solid state image pickup device, when photoelectric conversion units S1 to Sn and amplifier units A1 to An receiving outputs of the photoelectric conversion units S1 to Sn output dark signals to vertical signal lines V1 to Vn, a pulse φr applied to a control terminal 105 takes the high potential so that the MOS transistors Qr1 to Qrn as the reset transistors turn on and the potentials at one ends of the clamp capacitors take the ground potential. Thereafter, when the photoelectric conversion units S1 to Sn and amplifier units A1 to An output photo-signals, the pulse φr applied to a control terminal 105 takes the low potential so that the MOS transistors Qr1 to Qrn turn off. When photo-outputs are output, the potentials at one electrodes of the clamp capacitors C1 to Cn on the sides of the MOS transistors Q1 to Qn change by an amount of (photo-output−dark output), and the potentials at the opposite electrodes of the clamp capacitors C1 to Cn also change by an amount of (photo-output−dark output) from the ground level. As a scanning circuit sequentially outputs pulses φh1 to φhn, signals stored in the clamp capacitors C1 to Cn are transferred to a common horizontal signal line 101 and output from an output terminal 102 of a buffer amplifiers 3. Similar to the device shown in FIG. 2, the horizontal signal line 101 takes the ground level at the high potential of a pulse φhr during a period between sequential outputs of the pulses φh1 to φhn from the scanning circuit.
In the conventional device shown in FIG. 1, when a signal is transferred from each of the sample/hold capacitor CT1 to CTn to the parasitic capacitor Ch of the horizontal signal line 101, a signal transmission gain at the n-stage of signal transfer is CTn/(CTn+Ch) which is smaller than 1. An S/N ratio is therefore lowered. The transmission gain and S/N ratio lower more as the number of pixels of the device is increased and the number of MOS transistors Qh1 to Qhn shown in FIG. 1 is increased, because this increase of the numbers results in increase of a total sum of the parasitic capacitances between the drain—back gate of the MOS transistors Qh1 to Qhn and the parasitic capacitances between the gate—drain and therefor the capacitance Ch increases.
FIG. 4 is a schematic diagram showing two parasitic capacitances of the capacitance Ch. Reference numeral 11 represents the gate of a MOS transistor, reference numerals 12 and 13 represent its source and drain regions, reference numeral 14 represents a bulk substrate, and reference numeral 15 represents an oxide layer. One capacitance constituting the capacitance Ch is a PN junction capacitance between the source region 12 and substrate 14 or between the drain region 13 and substrate 14. If the transistor shown in FIG. 4 is an NMOS transistor, the bulk substrate is generally connected to a ground electrode so that the PN junction capacitance is formed relative to the ground line.
The other capacitance constituting the capacitance Ch is a capacitance having the oxide layer as its dielectric layer in the overlapped areas 21 and 22 shown in FIG. 4 between the gate 11 and source/drain 12, 13.
The overlapping parasitic capacitances between the gate and drain/source of the MOS transistors Qh1 to Qhn shown in FIG. 1 constitute the capacitance Ch. The gates of the MOS transistors Qh1 to Qhn are driven by the scanning circuit which are a gate circuit made of CMOS inverters or the like. Therefore, one electrode (gate) of the overlapping capacitance between the gate and drain/source is connected via an on-resistance of the driver gate circuit of CMOS inverters or the like to the high potential power source or low potential power source (generally ground potential) of this circuit.
FIG. 5 is a schematic diagram showing a MOS transistor Qhn and a portion of a scanning circuit. In FIG. 5, like elements and pulses to those shown in FIG. 1 are represented by using identical reference symbols.
In FIG. 5, Qhn represents a MOS transistor as a switch for transferring a signal from a capacitor CTn to a capacitor Ch, 101 represents a horizontal signal line, and Lhn represents a signal line for controlling on/off of the MOS transistor Qhn. The capacitor Ch is constituted of an overlapping parasitic capacitor 35 between the gate and source/drain of the MOS transistor Qhn and a PN junction parasitic capacitor 36 between the drain and substrate of the transistor Qhn. A CMOS inverter in the scanning circuit for driving the gate of the MOS transistor Qhn is made of a PMOS transistor 32 and an NMOS transistor 33. The CMOS inverter is powered by a high potential power source 31.
The conventional device shown in FIG. 3 has also a similar problem. When signal charges in the clamp capacitors C1 to Cn are transferred to the parasitic capacitor Ch of the common horizontal signal line 101, the signal transfer gain is lowered to Cn/(Cn+Ch).
FIG. 6 is a schematic diagram showing another conventional MOS type solid state image pickup device. As shown in FIG. 6, sensor cells 1 are two-dimensionally disposed in a matrix shape. The sensor cell 1 is activated or reset by a signal 2 (2-1, 2-2, . . . ) supplied from a vertical shift resister 11.
The output terminal of each sensor cell 1 is connected to a vertical signal line 5 (5-1, 5-2, . . . , 5-n). A signal voltage generated in the sensor cell 1 appears on this vertical signal line 5 and is stored in a clamp capacitor 3 (3-1, 3-2, . . . , 3-n) in the form of electric charges. In many cases, fluctuation in the signal charges generated in the sensor cells 1 is cancelled by unrepresented switches, capacitors and the like. By sequentially turning on horizontal select switches 4 (4-1, 4-2, . . . , 4-n) by horizontal select signals 7 (7-1, 7-2, . . . , 7-n) supplied from a horizontal shift register 12, signal charges in the clamp capacitors 3 are transferred via a horizontal signal line 6 to the inverting input terminal of a differential amplifier 9 having a negative feedback capacitor 8 and output from an output terminal 13 in the form of voltage. The non-inverting input terminal of the differential amplifier 9 is connected to a reference voltage source 10.
In this solid state image pickup device, the horizontal select switch 4 is generally made of a MOS transistor. For example, an NMOS transistor such as shown in FIG. 7 is used as the horizontal select switch 4. In FIG. 7, reference numeral 21 represents a gate, reference numeral 22 represents source and drain diffusion regions made of n-type semiconductor, reference numeral 23 represents a p-type well diffusion region, and reference numeral 25 represents an oxide layer. As seen from FIG. 7, a PN junction capacitor is formed between the source/drain region 22 and the p-type well region 23. Since the p-type well region 23 is generally connected to the lowest ground potential in a semiconductor integrated circuit, the source/drain region 22 has a PN junction capacitor using the ground as its one electrode (this PN junction capacitance is represented by Cj hereinafter). Reference numeral 24 represents overlapped areas between the gate 21 and source/drain regions 22 caused by lateral diffusion of the source/drain regions. A so-called overlapping capacitance (hereinafter represented by Cov) is therefore formed between the gate 21 and source/drain region by using the gate oxide layer 25 as the capacitor dielectric layer.
The horizontal signal line 6 shown in FIG. 6 has capacitors 15 and 16 shown in the equivalent circuit of FIG. 8 because the horizontal select switches have the above-described parasitic capacitances Cj and Cov. The equivalent circuit shown in FIG. 8 corresponds to a signal transmission path from the vertical signal lines to the output terminal 12 shown in FIG. 6.
Referring to FIG. 8, reference numeral 5 (5-1, 5-2, . . . , 5-n) represents a vertical signal line, reference numeral 3 (3-1, 3-2, . . . , 3-n) represents a clamp capacitor, reference numeral 4 (4-1, 4-2, . . . , 4-n) represents a horizontal transfer switch, reference numeral 6 represents a horizontal signal line, reference numeral 7 (7-1, 7-2, . . . , 7-n) represents a horizontal select line of a horizontal shift register 12, reference numeral 8 represents a negative feed back capacitor of an output amplifier 9 for converting a signal charge into a voltage signal, and reference numeral 14 (14-1, 14-2, . . . , 14-n) represents an output impedance of a drive gate in the shift resister 12 for driving the horizontal select line 7. In the example shown in FIG. 8, the horizontal transfer switch 4 is made of an NMOS transistor. At an “L” level of the horizontal select line 7 at which level the horizontal transfer switch turns off, the drive gate has the output impedance 14 relative to the ground. Reference numeral 15 (15-1, 15-2, . . . , 15-n) represents a PN junction parasitic capacitor between the source and well of the NMOS transistor of the horizontal transfer switch 4. Reference numeral 16 (16-1, 16-2, . . . , 16-n) represents an overlapping capacitor between the gate and source of the NMOS transistor 4. As seen from FIG. 8, the horizontal signal line 6 has the total capacitor Ctot=n×(Cj+Cov) where n is the number of vertical signal lines of the solid state image pickup device. If the total number of pixels of the solid state image pickup device is several hundred thousands to several millions, the parasitic capacitance Ctot becomes as large as several pF to several tens pF. This parasitic capacitance Ctot is driven by the output amplifier 9. The equivalent circuit including the capacitance Ctot as viewed from the output amplifier 9 is shown in FIG. 9.
In FIG. 9, reference numeral 9 represents an output amplifier, reference numeral 8 represents a negative feedback capacitor, r0 represents an equivalent output impedance of the output amplifier 9, and VN represents an input referred random noise source of the output amplifier 9. Therefore, the output amplifier 9 shown in FIG. 8 is an ideal amplifier having the output impedance of 0 and a random noise of 0. A transmission function from the output of the output amplifier 9 to its inverting input terminal (−) is represented by:(1/SCtot)/(1/SCN)+(1/SCtot)+r0))=CN/(CN+Ctot+SCN·Ctot·r0)where S ia a Laplace operator and CN is a capacitance value of the negative feedback capacitor 8.
As apparent from this equation, the transmission function takes the form of a low-pass filter whose cut-off frequency is influenced by the value of the parasitic capacitance Ctot. Therefore, the bandwidth of the output amplifier 9 is narrowed by the parasitic capacitance Ctot and the output drive speed lowers.
Furthermore, random noises (VN) of the output amplifier is amplified by the parasitic capacitance Ctot(VN×(Ctot/CN)).